Fishing – trapping – and vermin destroying
Patent
1996-02-20
1997-02-25
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437200, 437247, H01L 21441
Patent
active
056058543
ABSTRACT:
A for forming an integrated titanium and tungsten polycide for deep submicron processing without bridging and having low resistance source/drain and gate materials is described. A gate electrode stack is formed by patterning layers of tungsten silicide overlying polysilicon overlying a gate silicon oxide on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrode as a mask. Spacers are formed on the sidewalls of the gate electrode. The substrate is annealed in an oxidizing ambient to drive in the lightly doped regions whereby a first silicon dioxide layer is formed overlying the gate electrode and a second silicon dioxide layer is formed overlying the semiconductor substrate wherein the first silicon dioxide layer is thicker than the second silicon dioxide layer. The second silicon dioxide layer is etched away whereby a portion of the first silicon dioxide layer remains. A layer of titanium is deposited over the surface of the substrate. A first RTA is performed to transform a portion of the titanium layer directly overlying the semiconductor substrate into titanium salicide and to transform the remaining titanium layer into titanium nitride. The titanium nitride layer is removed. A second RTA is performed to stabilize the titanium salicide layer. Heavily doped source and drain regions are implanted completing the fabrication of the integrated circuit device.
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patent: 5352631 (1994-10-01), Sitaram et al.
patent: 5411906 (1995-05-01), Johnson et al.
S. Wolf, "Silicon Processing for the VLSI Era-vol. 1" Lattice Press, Sunset Beach, CA. 1986, pp. 397-399.
Chaudhari Chandra
Pike Rosemary L. S.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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