Integrated circuit with improved off chip drivers

Details Integrated circuit with improved off chip drivers Integrated circuit with improved off chip drivers

1998-06-09

2000-10-24

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 17, 326 27, 326101, H03K 190185

Patent

active

061373168

ABSTRACT:
An array of multiple off chip drivers on an integrated circuit (IC) chip has reduced synchronous switching output timing error (TSSO) at high speeds of operation. The array includes a pair of low resistance buses to provide charge and discharge paths for the outputs, a plurality of terminals connecting the respective drivers between the buses, the resistance of each terminal being substantially greater than the resistance of either bus, and a plurality of capacitors connected internally of the respective drivers. Each driver has an input for receiving binary data from a memory unit and an output terminal which is switched in accordance with the binary input data to a higher or lower voltage level. There are a plurality of transistor switches within each driver which selectively couple a capacitor to the output terminal when it is driven high and at the same time couple another capacitor to one of the buses, and vice versa when the output terminal is driven low.

REFERENCES:
patent: 4812684 (1989-03-01), Yamagiwa et al.
patent: 5198699 (1993-03-01), Hashimoto et al.
patent: 5309040 (1994-05-01), Nakano et al.
patent: 5428311 (1995-06-01), McClure
patent: 5786709 (1998-07-01), Kirsch et al.
patent: 5861764 (1999-01-01), Singer et al.
PCT Publication No. WO 96/41443, Dec. 19, 1996.

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