Semiconductor metalization system and method

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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257773, 257774, H01L 2348, H01L 2352, H01L 2940

Patent

active

061371785

ABSTRACT:
A method for forming a metalization system is provided. The method includes providing a substrate. A dielectric layer is formed over a surface of the substrate. A plurality of via holes is formed into a surface and the dielectric layer, such holes passing through the dielectric layer. Recesses are formed in the surface of the dielectric layer, such recesses terminating in a portion of the plurality of via holes passing through the dielectric layer. A metalization layer is deposited over the surface of the dielectric layer, portions of the metalization layer passing through the via holes, portions of the metalization layer being disposed in the recesses and portions of the metalization layer being disposed on the surface of the dielectric layer. The metalization layer is patterned into a plurality of conductors, one portion of the conductors being disposed on one level of the dielectric layer and another portion of the conductors disposed in the recesses. A metalization system having a substrate with a dielectric layer disposed over such substrate. A plurality of electrical conductors is provided, one portion of the conductors being disposed on one level of the dielectric layer and another portion of the conductors being recessed in a surface portion of the dielectric layer.

REFERENCES:
patent: 5471093 (1995-11-01), Cheung
patent: 5691574 (1997-11-01), Suzuki
patent: 5702982 (1997-12-01), Lee et al.
patent: 5739587 (1998-04-01), Sato
patent: 5753976 (1998-05-01), Harvey
PCT Publication No. W0 97/47036, International Applcn. No. PCT/US97/02513 filed Feb. 18, 1997.
Publication entitled "Dual Damascene: A ULSI Wiring Technology" by Kaanta et al., pp. 144-152.

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