Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

365201, 36518907, 36523001, G11C 700, G11C 800

Patent

active

055008216

ABSTRACT:
A semiconductor memory device where the sequence of addresses in an access operation is predetermined, comprises a memory cell array with a redundant section, a data latch circuit for writing and reading into and from the memory cell array, and a redundant-section select circuit for storing the address one cycle before a cycle in which accessing is effected according to the address of a defective memory cell, comparing what is stored with the input address signal, and outputting relief information indicating whether they coincide with each other, wherein the relief information from the redundant-section select circuit is outputted after one cycle at the same time that the address signal is switched. This makes it possible to relieve defective memory cells without lengthening the access time, thereby enabling high-speed data input and output.

REFERENCES:
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patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4989181 (1991-01-01), Harada
patent: 5278794 (1994-01-01), Tanaka et al.
patent: 5307316 (1994-04-01), Tavemag
patent: 5359559 (1994-10-01), Nomura et al.

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