Semiconductor memory device having initialization transistor

Details Semiconductor memory device having initialization transistor Semiconductor memory device having initialization transistor

1986-06-02

1988-10-11

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365189, 365190, 307571, G11C 700, G11C 1140

Patent

active

047776234

ABSTRACT:
A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.

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Lee et al., "Control Logic and Cell Design for a 4K NVRAM" IEEE Journal of Solid-State Circuits SC-18, No. 5 (Oct. 1983): 525-532.
Chao, "Static RAM with Nonvolatile Backup Memory", IBM Technical Disclosure Bulletin vol. 24, No. 5 (Oct. 1981) 2456-2457.
Texas Instruments specification sheet for a Dual D-Type Positive-Edge-Triggered Flip-Flops with Clear and Preset.

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