Sequential read access of serial memories with a user defined st

Details Sequential read access of serial memories with a user defined st Sequential read access of serial memories with a user defined st

1988-01-28

1989-10-10

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

With shift register

36523009, 365 78, 377 76, G11C 700, G11C 800

Patent

active

048736716

ABSTRACT:
Circuitry for serial read memory access utilizing a random starting address is disclosed. Fast read access is provided without upsetting the original data pattern stored in the memory core if the sequential read is terminated in midstream. After the last memory address is reached, the access automatically rolls over to the first address. The circuit provides both random and sequential access functions and allows the memory to be used as a shift register of variable length.

REFERENCES:
patent: 4138732 (1979-02-01), Suzuki et al.
patent: 4236255 (1980-11-01), Jansen et al.
patent: 4422160 (1983-12-01), Watanabe
patent: 4507760 (1985-03-01), Fraser
patent: 4646270 (1987-02-01), Voss
patent: 4751684 (1988-06-01), Holt

Affiliated with

Also associated with

Rating

Sequential read access of serial memories with a user defined st does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sequential read access of serial memories with a user defined st, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sequential read access of serial memories with a user defined st will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1961805