Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1994-12-27

1996-09-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

36518529, 365218, 36523003, 36523008, G11C 700

Patent

active

055530265

ABSTRACT:
The non-volatile memory device comprises a memory cell array, a block decoder, and a decode signal reading section. The memory cell array has a plurality of cell blocks. Each of the cell blocks is composed of a plurality of memory cells arranged roughly into a matrix pattern. Each memory cell has a floating gate to or from which electrons are injected or extracted to write or erase data. The block decoder receives a block address, and outputs a decode signal to select a cell block corresponding to the block address from the cell blocks. The memory cells of the selected block are erased simultaneously. When a control signal is inputted to the block decoder, the block decoder outputs the decode signal to select all the cell blocks for erasure of the memory cells of all the cell blocks simultaneously, irrespective of the block address. The decode signal reading section outputs the decode signal to the outside. The decode signal is applied to the cell blocks and in parallel to the decode signal reading section itself and further outputted to the outside therethrough. In the memory device, the block erase function can be checked at a short time and additionally the other functional blocks can be checked simply.

REFERENCES:
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5274596 (1993-12-01), Watanabe
patent: 5301162 (1994-04-01), Shimizu
patent: 5367495 (1994-11-01), Ishikawa
patent: 5418742 (1995-05-01), Asano
International Search Report dated May 18, 1995, appl. No. 94120818.3.

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