Distortion reduction circuit for analog to digital converter sys

Details Distortion reduction circuit for analog to digital converter sys Distortion reduction circuit for analog to digital converter sys

1994-06-30

1996-09-03

Williams, Howard L.

Coded data generation or conversion

Sample and hold

341156, 327 96, H03M 114

Patent

active

055527841

ABSTRACT:
An analog to digital (A/D) converter apparatus is disclosed which increases spurious free dynamic range without adding a significant amount of noise. The apparatus includes a sample and hold circuit, a main range A/D converter for converting the sample and hold circuit output into a first digital signal, and a digital to analog (D/A) converter for converting the output of the main range A/D converter to an analog signal which is fed to a summing node. The output of the sample and hold circuit is also fed to the summing node through a first load resistor. The difference between the D/A output and the sample and hold output is generated at the summing node, and this difference is amplified and digitized by a subrange A/D converter. Added circuitry including a bootstrap amplifier and second load resistor are provided to increase the load impedance on the sample and hold output. An embodiment making use of multiple sample and hold circuits connected in parallel using a bootstrap amplifier is also disclosed.

REFERENCES:
patent: 4814722 (1989-03-01), Hartmann et al.
patent: 4862171 (1989-08-01), Evans
patent: 4885545 (1989-12-01), Sanielevici
patent: 4894656 (1990-01-01), Hwang et al.
patent: 4896155 (1990-01-01), Craiglow
patent: 5099240 (1992-03-01), Nakatani et al.
patent: 5243235 (1993-09-01), Wakayama et al.
patent: 5248973 (1993-09-01), Babu et al.

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