Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Patent
1995-06-07
1996-09-03
Young, Brian K.
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
341 77, H03M 300
Patent
active
055527850
ABSTRACT:
A method and apparatus for phase locking to an input signal and outputting a sigma-delta modulated control signal. The method and apparatus of the present invention provide a sigma-delta modulated control signal which can be utilized by any one of a decimator for decimating a digital data at a first data to a digital data at a second data rate and an interpolator for interpolating a digital data at a first data rate to a digital data at a second data rate. The decimator and the interpolater can be utilized in any one of an analog-to-digital converter, a digital-to analog converter and a digital-to digital converter. In one embodiment, a period of the input signal is determined and fed to a phase-locked loop which includes a sigma-delta modulator for providing the sigma-delta modulated control signal. The phase-locked loop also includes a phase detector for determining a phase and a frequency-difference between the input signal and a conversion signal generated by the phase-locked loop. The method and apparatus thus locks to the phase and the frequency of the input signal and provide a phase-locked sigma-delta-modulated control signal.
REFERENCES:
patent: 4179670 (1979-12-01), Kingsbury
patent: 4281318 (1981-07-01), Candy et al.
patent: 4797845 (1989-01-01), Stikvoort
patent: 4953117 (1990-08-01), Lagadec
patent: 4954824 (1990-09-01), Yamada et al.
patent: 4987373 (1991-01-01), Soo
patent: 4990911 (1991-02-01), Fujita et al.
patent: 5075679 (1991-12-01), Gazsi
patent: 5111417 (1992-05-01), Belloc et al.
patent: 5119093 (1992-06-01), Vogt et al.
patent: 5121065 (1992-06-01), Wagner
patent: 5157395 (1992-10-01), Del Signore et al.
patent: 5204827 (1993-04-01), Fujita et al.
patent: 5227787 (1993-07-01), Kurashina
patent: 5313205 (1994-05-01), Wilson
patent: 5353026 (1994-10-01), Wilson
J. Janssen, et al. A New Principle/IC for Audio Sampling Rate Conversion, presented at the 96th Convention, Feb. 26, 1994-Mar. 1, 1994.
Richard J. Higgins, Digital Signal Processing in VLSI, Prentice Hall, Englewood Cliffs, NJ 07632, 1990, pp. 29-31.
Douglas F. Elliott, et al, Fast Transforms, Algorithms, Analyses, Applications, 1982, Academic Press, p. 13.
Paul J. Hurst, et al. A Programmable Clock Generator Using Noise Shaping and Its Application in a Switched-Capacitor Filter, Solid State Circuits Research Laboratory, Dept. of Electrical and Computer Engineering, University of California, Davis (two pages), no date of reference available.
Electronique, No. 24, Jan. 1993, Paris, France, pp. 42-44, Trazequet, H., "Les CAN Delta-Sigma Deviennent Progammables".
Patent Abstracts of Japan, vol. 003, No. 018 (E-091) Feb. 16, 1979 & JP-A-53147409 (Fujitsu Ltd.) Dec. 22, 1978.
International Search Report From International Patent Application, PCT/US94/10269 Filed Sep. 13, 1994.
Cellini Ronald A.
Wilson James
Analog Devices Inc.
Young Brian K.
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