Output buffer circuit having gate voltage control circuit of gat

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

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H03K 190948

Patent

active

055527191

ABSTRACT:
The output buffer circuit according to the present invention comprises: a P-channel type output transistor which is provided between a first power supply terminal and an output terminal and receives an input signal at a gate thereof; an N-channel type transistor which is provided between the output terminal and a second power supply and has a gate connected to a drain of a gate current controlling transistor; a circuit for supplying the input signal to a source of the gate current controlling transistor; and a voltage control generation circuit which generates as a gate voltage of the gate current controlling transistor a first voltage value which is smaller than a value of the power supply voltage for a predetermined time, and further generates a second voltage value which is higher than the first voltage value after the elapse of the predetermined time.

REFERENCES:
patent: 5111076 (1992-05-01), Tarng
patent: 5194764 (1993-03-01), Yano et al.
patent: 5233238 (1993-08-01), Mattos
patent: 5237213 (1993-08-01), Tanoi

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