Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-04-24
1999-02-09
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257301, 257310, 257311, H01L 27108, H01L 2976, H01L 31119
Patent
active
058698604
ABSTRACT:
A method for producing a capacitor having a dielectric and first and second capacitor electrodes in a semiconductor circuit device formed on a semiconductor substrate, includes forming a trench in a layer applied to the substrate. An electrically conductive layer for the second capacitor electrode is deposited inside the trench and at least regionally conformally with side walls thereof. An auxiliary layer acting as a space-holder for the dielectric is conformally deposited inside the trench and on the electrically conductive layer for the second capacitor electrode. An electrically conductive layer for the first capacitor electrode is conformally deposited inside the trench and on the auxiliary layer. The auxiliary layer is at least partial removed to expose a hollow layer in at least a partial region between the two electrically conductive layers for the first and second capacitor electrodes. The dielectric is deposited into the exposed hollow layer between the two electrically conductive layers. A semiconductor memory device and a method for producing the device include producing the capacitor after production of the transistor and metallizing layers associated therewith for connection of the word and bit lines, in a configuration projecting upward from the plane; placing the capacitor in a trench formed inside a contact metallizing layer for the second electrode terminal of the transistor; and setting a depth of the trench to be equivalent to a layer thickness of the metallizing layer.
REFERENCES:
patent: 5101251 (1992-03-01), Wakamiya et al.
patent: 5262343 (1993-11-01), Rhodes et al.
patent: 5567964 (1996-10-01), Kashihara et al.
"Ferroelectrics an high Permittivity Dielectrics for Memory Applications" (Larsen et al.), dated Aug. 1993, Microelectronic Engineering, No. 1/4, Amsterdam, pp. 53-60.
"Integration of Ferroelectric Capacitor Technology with CMOS" (Moazzami et al.), 1994 Symposium on VLSI Technology Digest of Technical Papers, pages 55-56.
"A 256kb Nonvolatile Ferroelectric Memory at 3V and 100ns" (Tatsumi et al.), 1994 ISSCC, Session 16, Technology Directions: Memory, Packaging, Paper FA 16.2, pp. 206-209 and 315-316.
"Recessed Memory Array Technology for a Double Cylindrical Stacked Capacitor Cell of 256M DRAM" (Sagara et al. ), dated Nov. 1992, IEICE Transactions on Electronics, vol. E75-C, No. 11.
Tempel Georg
Widmann Dietrich
Greenber Laurence A.
Lerner Herbert L.
Ngo Ngan V.
Siemens Aktiengesellschaft
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