Redundancy-secured semiconductor memory

Details Redundancy-secured semiconductor memory Redundancy-secured semiconductor memory

1984-02-13

1986-08-12

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Bad bit

365 96, G11C 1140

Patent

active

046060138

ABSTRACT:
A redundancy-secured semiconductor memory including a matrix of regular memory cells consisting of a plurality of regular memory cell trains, an extra memory cell train for redundant construction, and a taking-over system for enabling the extra memory cell train to take over the function of a faulty regular memory cell train including a faulty bit, wherein the taking-over system comprises a decoder and a monostable latching circuit connected to the decoder through a current conducting element capable of breakage in response to when one of the regular memory cell trains comes to include a faulty bit, thereby enabling the monostable latching circuit to fix its output to the low logic potential. Thus, the faulty regular memory cell train is kept in an unselected state without DC power consumption.

REFERENCES:
patent: 3765002 (1973-10-01), Basse
patent: 4459685 (1984-07-01), Sud et al.
Schuster, "On-Chip Redundancy Scheme", IBM Technical Disclosure Bulletin, vol. 14, No. 5, Oct. 1971, pp. 1513-1514.
Tolley et al., "72K RAM Stands Up to Hard and Soft Errors", Electronics, vol. 55, No. 12, Jun. 16, 1982, pp. 147-151.
Fitzgerald et al., "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM Journal of Research Development, vol. 24, No. 3, May 1980, pp. 291-298.

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