Semiconductor integrated circuit device having a test mode setti

Details Semiconductor integrated circuit device having a test mode setti Semiconductor integrated circuit device having a test mode setti

1995-02-15

1996-09-24

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Testing

36523008, G11C 700

Patent

active

055597440

ABSTRACT:
A semiconductor integrated circuit device includes a test mode setting circuit. The test mode setting circuit includes an AND circuit for deriving the logical AND of a test mode setting permission signal and a signal input from a pin, and a latch circuit which is set by an output of the AND circuit and reset by a test mode setting release signal. After the test content is latched in the latch circuit in response to a test mode setting permission signal, the test is effected according to the setting of state of the semiconductor integrated circuit device and data latched in the latch circuit.

REFERENCES:
patent: 4580246 (1986-04-01), Sibigtroth
patent: 5373472 (1994-12-01), Ohsawa
patent: 5452253 (1995-09-01), Choi
IEEE. Journal of Solid-State Circuits, vol. SC-22, No. 5; Oct. 1987, pp. 669-675, N. Ohtsuka et al., "A 4-Mbit CMOS EPROM".

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