Integrated circuit structure having at least one CMOS-NAND gate

Details Integrated circuit structure having at least one CMOS-NAND gate Integrated circuit structure having at least one CMOS-NAND gate

1994-11-01

1996-09-24

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257331, 257337, 257369, 326106, H01L 27092, H01L 2978

Patent

active

055593534

ABSTRACT:
A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

REFERENCES:
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4566025 (1986-01-01), Jastrzebski et al.
patent: 4788158 (1988-11-01), Chatterjee
patent: 4810906 (1989-03-01), Shah et al.
patent: 5138197 (1992-08-01), Kuwana
patent: 5311050 (1994-05-01), Nitayama et al.
"Modular Approach to C-MOS Technology Tailors Process to Application," Kokkonen et al., Electronics, May 3, 1994, pp. 129-133.
"Complex 3D CMOS Circuits Based on a Triple-Decker Cell," Roos et al., IEEE J. of Solid-State Cir., vol. 27, No. 7, Jul. 1992, pp. 1067-1072.
"Einsatz von Deltadotierschichten fur die Silizium-Nanoelektronik," Kiunke, 1992, pp. 2-3.

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