Dynamic random access memory device with internal refresh

Details Dynamic random access memory device with internal refresh Dynamic random access memory device with internal refresh

1988-01-05

1989-09-26

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

36523008, 36518911, 365226, G11C 700, G11C 1140

Patent

active

048706205

ABSTRACT:
The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1. Therefore, malfunctions of the address buffer 1 can be prevented.

REFERENCES:
patent: 4207618 (1980-06-01), White, Jr. et al.
patent: 4570242 (1986-02-01), Nagami
patent: 4628482 (1986-12-01), Tachiuchi et al.
patent: 4631701 (1986-12-01), Kappeler et al.
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 4682306, Sakurai et al.
Eaton, S. Sheffield, IEEE International Solid State Conference, "A 5V-only 2Kx8 Dynamic Ram", Feb. 15, 1987, pp. 144-145.
Ford, David C. et al, Electronics, "64-K Dynamic RAM Has Pin That Refreshes", Feb. 15, 1979, pp. 141-147.

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