Semiconductor memory device having data bus reset circuits

Details Semiconductor memory device having data bus reset circuits Semiconductor memory device having data bus reset circuits

1987-09-16

1989-09-26

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

For complementary information

36518901, 36523006, G11C 1140, G11C 1300

Patent

active

048706175

ABSTRACT:
A semiconductor memory device comprises a plurality of reset circuits connected to a data bus pair at different locations. Before each read operation, the reset circuits reset the data bus pair to a predetermined reset voltage. The resetting of the data bus pair is virtually unaffected by the distributed resistances and parasitic capacitances of the data bus pair, since the resetting is carried out at a plurality of locations on the data bus pair.

REFERENCES:
patent: 4578776 (1986-03-01), Takemae et al.
patent: 4584670 (1986-04-01), Michael
patent: 4589096 (1986-05-01), Kaneko et al.
patent: 4601017 (1986-07-01), Mochizuki et al.

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