Series/parallel/series shift register memory system

Details Series/parallel/series shift register memory system Series/parallel/series shift register memory system

1983-06-06

1986-04-22

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Sipo/piso

365 1, 365 78, 365200, 371 36, 371 38, G11C 1908, G11C 1928

Patent

active

045846731

ABSTRACT:
A series/parallel/series shift register memory system having storage positions provided on a substrate. In addition to the single parallel-connected storage registers required to achieve the nominal storage capacity, there are provided groups of first and second nominally redundant single storage registers. The first redundant registers are used as substitutes for faulty single storage registers, so that the nominal storage capacity can be maintained. The second redundant registers are used for the transport of redundant code data. Also provided is a multi-state sequencer for indicating, in each state, the information to be carried by a particular group of storage registers and for forming, on the basis of this information, an error-detecting or error correction code which is carried by the second redundant storage registers. Faulty storage registers can thus be pin-pointed, after which dummy information is automatically inserted in the input information at locations which are such that it will nominally be carried by the faulty registers, thus effectively substituting a first redundant register for each faulty register. The system is thus self-healing.

REFERENCES:
patent: 3675200 (1972-07-01), Bossen et al.
patent: 4073012 (1978-02-01), Ohnigian et al.
patent: 4092734 (1978-05-01), Collins et al.
patent: 4404673 (1983-09-01), Yamanouchi

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