Decoder for suppressing error propagation

Details Decoder for suppressing error propagation Decoder for suppressing error propagation

1997-01-22

2000-02-15

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714799, G06F 1110, H03M 1312

Patent

active

060265078

ABSTRACT:
The present invention provides a method and apparatus for suppressing error propagation. A decoder comprises a plurality of product-sum arithmetic units each for performing a predetermined product-sum operation for a value of an input signal. An inside-outside judging means judges whether the result of the operation performed by each of the plurality of product-sum arithmetic units is within a predetermined range and outputs an inside-outside judgment. A selecting means selects the predetermined range, based on a known bit sequence and a coding method. An error judging means judges whether the selecting means selected an incorrect range, using the selected predetermined range, the inside-outside judgment, and the value of the input signal. The present invention can prevent mistakes in selecting the predetermined range and also prevent differences between the decoded and original data from influencing a subsequent bit sequence.

REFERENCES:
patent: 4945538 (1990-07-01), Patel
patent: 5748023 (1998-05-01), Hassner et al.
"A New Digital Signal Processing Channel For Data Storage Products" by A. Patel EEE Transactions on Magnetics vol. 27, No. 6, Nov. 1991.
"A Closed Set Of Normal Orthogonal Functions" By J. Walsh.

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