Lightly doped drain formation integrated with source/drain forma

Details Lightly doped drain formation integrated with source/drain forma Lightly doped drain formation integrated with source/drain forma

1998-04-06

2000-05-30

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257408, 257411, H01L 2976, H01L 2994

Patent

active

060693878

ABSTRACT:
An integrated circuit fabrication process is provided for forming a transistor in which the source/drain areas are formed simultaneously with the lightly doped drain areas. A gate electrode including a high-K gate dielectric and a gate conductor is formed upon a semiconductor substrate. The high-K gate dielectric is then selectively narrowed relative to the gate conductor. The source/drain areas and lightly doped drain areas are formed using a single impurity implant without the need for sidewall spacers on the gate electrode. A metal silicide layer may be formed across upper surfaces of the gate conductor and source/drain areas, also without the need for sidewall spacers on the gate electrode.

REFERENCES:
patent: 5614739 (1997-03-01), Abrokwah et al.
patent: 5767531 (1998-06-01), Yoshinouchi
patent: 5929493 (1999-07-01), Gardner et al.
patent: 5969394 (1999-10-01), Gardner et al.

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