Programmable switch matrix and method of programming

Details Programmable switch matrix and method of programming Programmable switch matrix and method of programming

1996-12-23

2000-02-15

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 44, H03K 19173

Patent

active

060257350

ABSTRACT:
A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.

REFERENCES:
patent: 4642487 (1987-02-01), Carter
patent: 4670749 (1987-06-01), Freeman
patent: 5361224 (1994-11-01), Takasu
patent: 5361225 (1994-11-01), Ozawa
patent: 5412596 (1995-05-01), Hoshiba
patent: 5519812 (1996-05-01), Ishihara
patent: 5600264 (1997-02-01), Duong et al.

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