System bus control system for multiprocessor system

Details System bus control system for multiprocessor system System bus control system for multiprocessor system

1993-10-29

1996-05-14

Auve, Glenn A.

395726, G06F 1300

Patent

active

055176259

ABSTRACT:
A system bus control system for a system has a plurality of first modules and at least one second module. The first and second modules are connected together via a system bus which is controlled by an arbiter receiving requests to use the system bus from the first and second modules. Each of the first modules includes a lock control signal supervising unit, a lock control signal outputting unit, a command outputting unit and a response receiving unit. Each of the second modules includes a lock control signal supervising unit, a source module information storing unit, a command receiving unit and a response outputting unit. The lock control is controlled by the first and second modules rather than the arbiter, which permits one of the first and second modules to use the system bus if the system bus is idle.

REFERENCES:
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4984153 (1991-01-01), Kregness et al.
patent: 5167022 (1992-11-01), Bahr et al.
patent: 5269005 (1993-12-01), Heil et al.
patent: 5353414 (1994-10-01), Iida et al.
patent: 5442755 (1995-08-01), Shibata

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