Method of making NMOS and PMOS LDD transistors utilizing thinned

Details Method of making NMOS and PMOS LDD transistors utilizing thinned Method of making NMOS and PMOS LDD transistors utilizing thinned

Filed on

1995-04-03

Date issued

1995-10-24

Examiner

Chaudhuri, Olik

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 56, 437 57, H01L 218232, H01L 218234, H01L 218238

Type

Patent

Status

active

Patent number

054609933

Description

ABSTRACT:
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit is described. A semiconductor substrate is provided wherein NMOS and PMOS regions are separated by an isolation region. Gate electrodes are formed in the NMOS and PMOS regions. Lightly doped regions are implanted into the semiconductor substrate within the NMOS and PMOS regions. A spacer material layer is deposited over the gate electrodes in the NMOS and PMOS regions and etched away to leave spacers on the sidewalls of the gate electrodes. The NMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the PMOS region. The photoresist mask is removed. After the PMOS implantation, a portion of the spacers is etched away to leave narrower spacers on the sidewalls of the gate electrodes. The PMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the NMOS region. The photoresist mask is removed and the fabrication of the integrated circuit is completed.

REFERENCES:
patent: 4642878 (1987-02-01), Maeda
patent: 4760033 (1988-07-01), Mueller
patent: 5091763 (1992-02-01), Sanchez
patent: 5296401 (1994-03-01), Mitsui et al.
"High Drivability and High Reliability MOSFETs with Non-Doped Poly-Sispacer LDD Structure" by A. Shimizu et al. Symposium of VLSI Tech. 1992, pp. 90-91.
"Double Spacer Technique for Titanium Self-Aligned Silicidation Technology," by W. D. Su et al, Symposium of VLSI Technology, pp. 113-116.

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