Programmable uniform symmetrical distribution logic allocator fo

Details Programmable uniform symmetrical distribution logic allocator fo Programmable uniform symmetrical distribution logic allocator fo

1995-06-02

1998-07-14

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 38, H03K 738, H03K 19177

Patent

active

057810303

ABSTRACT:
A programmable uniform distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable uniform distribution logic allocator provides a uniform number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable uniform distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product term-clusters, to a programmably selected logic macrocell. Specifically, the programmable uniform distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected to an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines. Also, each programmable router element is programmably connectable to and disconnectable from each of input lines connected to the plurality of programmable router elements so that each output line has access to all input signals on the plurality of input lines.

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Elektor Electronics, vol. 20, No. 227, issued 1 Nov. 1994, pp. 8-11, XP00047991 "Low Cost ispLSI Programmer".

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