Non-volatile semiconductor memory elements

Details Non-volatile semiconductor memory elements Non-volatile semiconductor memory elements

1980-09-02

1982-11-23

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

357 23, 357 54, 365182, G11C 1140

Patent

active

043609007

ABSTRACT:
The invention is embodied in a non-volatile metal-insulator-semiconductor having a novel combination of insulating layers including a silicon nitride layer covered by a silicon dioxide layer covered by a high dielectric constant insulator. In one embodiment of the invention the nitride layer is directly upon the semiconductor. In another embodiment the insulator combination also includes a second layer of silicon dioxide located between the nitride layer and the semiconductor. Writing is accomplished by injection of charge into the nitride layer and shifting the threshold voltage of the structure. Erasure is accomplished by forcing the injected charge back into the semiconductor to recombine with majority carriers. The charge can be electrons or holes depending on the semiconductor type. The memory element of the invention has lower write/erase voltages, shorter write/erase times and higher writing efficiency.

REFERENCES:
patent: 3479237 (1969-11-01), Bergh et al.
patent: 3967310 (1976-06-01), Horiuchi et al.
patent: 4024562 (1977-05-01), Brown et al.
patent: 4112507 (1978-09-01), White et al.
patent: 4151537 (1979-04-01), Goldman et al.
Chang, "Method for Forming A Flat SiO.sub.2 Topology in Multilevel Structures," IBM Tech. Disc. Bul., vol. 22, No. 2, 7/79, pp. 543-544.

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