Enhanced DRAM with single row SRAM cache for all device read ope

Details Enhanced DRAM with single row SRAM cache for all device read ope Enhanced DRAM with single row SRAM cache for all device read ope

1995-06-02

1998-02-24

Swann, Tod R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36518904, 36518905, G06F 1200

Patent

active

057218625

ABSTRACT:
An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register. Additionally, the row registers/memory cache is sized to contain a row of data of the DRAM array. Furthermore, a single column decoder addresses corresponding locations in both the memory cache and the DRAM array. And finally, all reads are only from the memory cache.

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