High speed nonvolatile memory cell

Details High speed nonvolatile memory cell High speed nonvolatile memory cell

1986-09-08

1988-05-31

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365185, G11C 700

Patent

active

047485930

ABSTRACT:
The circuit and structure of a direct write differential nonvolatile memory cell. The features of the cell include high speed read sensing, write without a prior erase operation, single polysilicon fabrication capability, and memory margining capabilities. The structural and functional symmetry maximizes cell density while providing complementary differential operation. In a preferred arrangement, the cell utilizes a pair of cross-coupled, capacitively complementary, centrally disposed floating gate electrodes. The cell is written directly by the provision of complementary signals on a pair of program lines, which lines are capacitively coupled to the floating gate electrodes. The data state of the cell is sensed by conduction in two bit lines, the conductive states of the lines being determined by the charge transferred onto the two floating gate electrodes during the simultaneous but complementary programming of such electrodes.

REFERENCES:
patent: 4288863 (1981-09-01), Adam
patent: 4348745 (1982-09-01), Schmitz
patent: 4467451 (1984-08-01), Moyer
Miyamoto et al., "An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 852-859.

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