High density flash EPROM

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257330, H01L 29788

Patent

active

057214425

ABSTRACT:
A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.

REFERENCES:
patent: 4929988 (1990-05-01), Yoshikawa
patent: 5338953 (1994-08-01), Wake
patent: 5459091 (1995-10-01), Hwang
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5508544 (1996-04-01), Shah
"High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs" by H. Takato et al, IEDM '88 pp. 222-224 No Date.

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