Semiconductor memory device for inputting and outputting data in

Details Semiconductor memory device for inputting and outputting data in Semiconductor memory device for inputting and outputting data in

1994-11-01

1996-07-09

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

36518903, 371 211, 371 213, 371 27, G11C 1134, H01L 2710

Patent

active

055351638

ABSTRACT:
A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.

REFERENCES:
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5138619 (1992-08-01), Fasang et al.

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