Arrangement and method of ascertaining memory addresses which ha

Details Arrangement and method of ascertaining memory addresses which ha Arrangement and method of ascertaining memory addresses which ha

1990-08-08

1992-06-30

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

36518908, 3652385, G11C 700, G11C 800

Patent

active

051269724

ABSTRACT:
Addresses of a main memory, which have been accessed by a central processing unit, are ascertained during the execution of a program stored in the main memory. A decoder is provided for receiving a predetermined number of lower n bits of main memory address bits and generates an output consisting of 2.sup.n bits (n is a positive integer). A memory includes a plurality of binary cells which correspond to memory cells of the main memory on a one by one basis. A logic circuit receives first and second data. The first data is the output of the decoder and the second data is one cell data retrieved from the memory. The logic circuit implements logical sum on the first and second data and superimposes the output thereof on the memory cell from which the second data has been derived. After the execution of the program is terminated, the contents of the memory are dumped.

REFERENCES:
patent: 4780855 (1988-10-01), Iida et al.
patent: 4796229 (1989-01-01), Greer, Jr. et al.
patent: 4878200 (1989-10-01), Asghar et al.
patent: 4926386 (1990-05-01), Park

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