Processor having a hierarchical control register file and method

Details Processor having a hierarchical control register file and method Processor having a hierarchical control register file and method

1995-09-12

1999-05-04

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing control

Processing sequence control

G06F 900

Patent

active

059000252

ABSTRACT:
A processor is provided with a number of control registers logically organized in a hierarchical manner. At the highest level is a set of control registers for controlling the overall system. At the second highest level are multiple sets of control registers for controlling concurrent execution of processes in multiple contexts. At the third highest level are multiple sets of control registers for controlling concurrent execution of multiple process threads for each of the concurrently executing contexts. Besides modifications resulting from the normal course of instruction execution, the control registers are directly accessible and modifiable using instructions of the standard instruction set. Each context/thread is assigned a variable privilege level for accessing and modifying control registers at the various levels. The instruction fetch unit is enhanced to dispatch instructions with appended context and tag identifications. The execution units are enhanced to verify a context/thread's privilege by locating the assigned privilege level using the appended context and thread identification information, before executing any instructions that access/modify a control register. Additionally, the execution units are further enhanced to be dynamically configurable in response to configuration control information stored in a thread level control register set for a thread and/or configuration information integrated with an instruction.

REFERENCES:
patent: 4038533 (1977-07-01), Dummermuth
patent: 4071887 (1978-01-01), Daly et al.
patent: 4354228 (1982-10-01), Moore et al.
patent: 4434461 (1984-02-01), Puhl
patent: 4488227 (1984-12-01), Miu et al.
patent: 4766566 (1988-08-01), Chuang
patent: 4965801 (1990-10-01), Dulac
patent: 5062073 (1991-10-01), Masuda et al.
patent: 5083263 (1992-01-01), Joy et al.
patent: 5159678 (1992-10-01), Wengelski et al.
patent: 5179530 (1993-01-01), Genusov et al.
patent: 5179702 (1993-01-01), Spix et al.
patent: 5313648 (1994-05-01), Ehlig et al.
patent: 5386563 (1995-01-01), Thomas
patent: 5398322 (1995-03-01), Marwood
patent: 5467459 (1995-11-01), Alexander et al.
patent: 5481719 (1996-01-01), Ackerman et al.
patent: 5493687 (1996-02-01), Garg et al.
patent: 5495615 (1996-02-01), Nizar et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5517648 (1996-05-01), Bertone et al.
patent: 5535404 (1996-07-01), Tsubota
patent: 5546554 (1996-08-01), Yung et al.
patent: 5553301 (1996-09-01), New et al.
patent: 5586275 (1996-12-01), Ehlig et al.
patent: 5611064 (1997-03-01), Maund et al.
patent: 5630102 (1997-05-01), Johnson et al.
Blinowski et al., "A Shared Memory Based on the Dataflow Paradigm", IEEE, Jan. 1995, pp. 68-75.
Tremblay et al., "A Three Dimensional Register File For Superscalar Processors", IEEE Proceedings of the 28th Annual Hawaii International Conference on System Sciences, 1995, pp. 191-201.
Motorola "Enhanced 32-bit microprocessor user's manual" 8-6 to 8-7 and 10-1 to 10-3, 1989.
DEC "DECchip 21064-AA Microprocessor Hardware reference manual" 3-1 to 3-2, 1992.

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