IC packaging lead frame for reducing chip stress and deformation

Details IC packaging lead frame for reducing chip stress and deformation IC packaging lead frame for reducing chip stress and deformation

1996-01-04

1998-06-30

Arroyo, T. M.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

257669, H01L 23495

Patent

active

057738785

ABSTRACT:
The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.

REFERENCES:
patent: 5637917 (1997-06-01), Tomita et al.
patent: 5661338 (1997-08-01), Yoo et al.

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