Semiconductor memory having redundancy circuit

Details Semiconductor memory having redundancy circuit Semiconductor memory having redundancy circuit

1997-09-25

2000-06-20

Phan, Trong

Static information storage and retrieval

Read/write circuit

Bad bit

36523001, G11C 700

Patent

active

060785349

ABSTRACT:
A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.

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"Fuseless Non-Volatile Ferroelectric Redundant Word and Bit Decoder", IBM Technical Disclosure Bulletin, vol. 34, No. 7B, Dec. 1, 1991, pp. 138-140.

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