Low dielectric semiconductor device with rigid lined interconnec

Details Low dielectric semiconductor device with rigid lined interconnec Low dielectric semiconductor device with rigid lined interconnec

1999-01-05

2000-06-20

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257522, 257506, 257554, 257754, 257758, 257774, 257638, 257756, 438584, 438421, 438422, 438319, 438614, H01L 2976, H01L 2994, H01L 2900

Patent

active

060780886

ABSTRACT:
Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.

REFERENCES:
patent: 5413962 (1995-05-01), Lur et al.
patent: 5708303 (1998-01-01), Jeng
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5798559 (1998-08-01), Bothra et al.

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