Method of fabricating a daul damascene structure

Details Method of fabricating a daul damascene structure Method of fabricating a daul damascene structure

1998-05-04

2000-06-20

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438634, 438637, 438638, 438669, 438671, H01L 214763

Patent

active

060777699

ABSTRACT:
A method is provided for fabricating a dual damascene structure on a substrate with a first dielectric layer, an etching stop layer, a second dielectric layer, and a hard mask layer formed on it. The first step is to define the hard mask layer in order to form the first hole, which corresponds to the position of the conductive layer exposing the second dielectric layer. Then, an etching process, including an etching step with medium SiO.sub.2 /SiN etching selectivity and an over-etching step with high SiO.sub.2 /SiN etching selectivity, is performed to form the second hole and the third hole. Finally, a glue/barrier layer and a metal layer are filled into the second hole and the third hole, thus accomplishing a dual damascene structure.

REFERENCES:
patent: 4764484 (1988-08-01), Mo
patent: 5635423 (1997-06-01), Huang et al.
patent: 5877076 (1999-03-01), Dai
patent: 5882996 (1999-03-01), Dai
patent: 5926732 (1999-07-01), Matsuura

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