Integrated circuit memory devices having variable block size era

Details Integrated circuit memory devices having variable block size era Integrated circuit memory devices having variable block size era

1997-09-12

1998-12-08

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1300

Patent

active

058479996

ABSTRACT:
Integrated circuit memory devices include circuits that can perform erase operations on multiple blocks of data simultaneously using preferred addressing techniques. The memory device contains blocks of memory cells and local decoders that are responsive to predecoded block address signals and electrically coupled a respective one of the blocks. A block size modifying circuit is electrically coupled to the local decoders and is responsive to a block size data signal and a first block address signal. The modifying circuit enables the simultaneous erasure of multiple blocks of memory cells during an erase time interval by generating the predecoded block address signals to select multiple ones of the local decoders simultaneously. The block size modifying circuit preferably comprises a block size decoder that is responsive to the block size data signal and an erase flag signal and performs the functions of decoding the block size data signal as a decoded block size data signal if the erase flag signal is in a first logic state and generating a modify disable signal if the erase flag signal is in a second logic state. A block address register performs the functions of passing the first block address signal as a second block address signal upon detection of the modify disable signal and generating a multi-block address erase signal upon detection of the decoded block size data signal. A block address predecoder performs the functions of generating the predecoded block address signal to select a single one of the plurality of local decoders upon detection of the second block address signal or select multiple ones of the plurality of local decoders upon detection of the multi-block address erase signal.

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