Non-uniform memory access (NUMA) data processing system that spe

Details Non-uniform memory access (NUMA) data processing system that spe Non-uniform memory access (NUMA) data processing system that spe

1998-10-01

2000-05-23

Follansbee, John A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711163, 711167, 712 28, 710104, G06F 1200

Patent

active

060676035

ABSTRACT:
A computer system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect, where each such request transaction specifies an associated datum. The node controller of the second processing node handles each speculatively transmitted request transaction received in response to a directory state of its associated datum.

REFERENCES:
patent: 5530933 (1996-06-01), Frink et al.
patent: 5603010 (1997-02-01), Dodd et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5673413 (1997-09-01), Deshpande et al.
patent: 5835950 (1998-11-01), Cho et al.
patent: 5940864 (1999-08-01), Arimilli et al.

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