Multilevel memory cell sense amplifier system

Details Multilevel memory cell sense amplifier system Multilevel memory cell sense amplifier system

1996-06-17

1997-11-04

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365205, 365208, G11C 1124

Patent

active

056847360

ABSTRACT:
A dynamic random access memory device stores two bits of digital data in each memory cell. Two sense amplifiers are provided to sense and reproduce any of the four binary values 11, 10, 01, 00 representing a strong one, a weak one, a weak zero and a strong zero, respectively, capable of being stored in each cell. The signal read out of a memory cell is restored to the memory cell by a feedback circuit which utilizes the outputs of the sense amplifiers. Thus the proper charge is replaced on the selected storage capacitor in the memory cell.

REFERENCES:
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patent: 5283761 (1994-02-01), Gillingham
patent: 5293563 (1994-03-01), Ohta
patent: 5532955 (1996-07-01), Gillingham
Masakazu Aoki, et al., "A 16-Levels/Cell Dynamic Memory", Feb. 1985, 1985 IEEE International Solid-State Circuits Conference, pp. 246-247.
David A. Rich, "A Survey of Multivalued Memories", Feb. 1986, IEEE Transactions on Computers, vol. C-35, No. 2, pp. 99-106.
Tohru Furuyama, et al., "An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application", Apr. 1989, IEEE Journal of Solid-State Circuits, vol. 24, No. 2, pp. 388-393.
Hideto Hidaka, et al., "A Divided/Shared Bitline Sensing Scheme for 64Mb DRAM Core", Feb. 1990, 1990 Symposium on VLSI Circuits, pp. 15-16.

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