Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-12-22
2000-05-23
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438637, 438639, 438738, 438740, H01L 214763
Patent
active
060665556
ABSTRACT:
A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and an device region, such as a source or drain, or some other layer or structure, and is an effective structure for small feature size structures, particularly self-aligned contact structures.
REFERENCES:
patent: Re35111 (1995-12-01), Liou et al.
patent: 4660276 (1987-04-01), Hsu
patent: 4806201 (1989-02-01), Mitchell et al.
patent: 4956312 (1990-09-01), Van Laarhoven
patent: 5037777 (1991-08-01), Mele et al.
patent: 5100838 (1992-03-01), Dennison
patent: 5164330 (1992-11-01), Davis et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5264391 (1993-11-01), Son et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5306952 (1994-04-01), Matsuura et al.
patent: 5364817 (1994-11-01), Lur et al.
patent: 5366929 (1994-11-01), Cleeves et al.
patent: 5378646 (1995-01-01), Huang et al.
patent: 5382483 (1995-01-01), Young
patent: 5384281 (1995-01-01), Kenney et al.
patent: 5466636 (1995-11-01), Cronin et al.
patent: 5482894 (1996-01-01), Havemann
patent: 5521121 (1996-05-01), Tsai et al.
patent: 5562801 (1996-10-01), Nulty
patent: 5569628 (1996-10-01), Yano et al.
patent: 5587331 (1996-12-01), Jun
patent: 5756396 (1998-05-01), Lee et al.
patent: 5759867 (1998-06-01), Armacost et al.
J. Givens et al., "Selective dry etching in a high density plasma for 0.5 .mu.m complementary metal-oxide-semiconductor technology," J. Vac. Sci. Technol. B 12(1), Jan./Feb. 1994, pp. 427-432.
K.K. Shih et al., "Hafnium dioxide etch-stop layer for phase-shifting masks," J. Vac. Sci. Technol. B 11(6), Nov./Dec. 1993, pp. 2130-2131.
Nulty James E.
Petti Christopher J.
Cypress Semiconductor Corporation
Gurley Lynne A.
Niebling John F.
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