Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-06-13
2000-05-23
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
700110, 702 83, 702181, G06F 1750, G06F 1100
Patent
active
060661798
ABSTRACT:
A method and apparatus to estimate properties of an integrated circuit device utilizes reduced resources. The representation of an integrated circuit is sampled using the statistical techniques of survey sampling. An average value of a property is determined from these samples and used to determine the property of the integrated circuit as a whole. Thus a property of an integrated circuit is determined from an analysis of a fraction of the integrated circuit representation. Error bounds associated with the property can be optionally determined from the estimated variance of the sampled property measurements. The method is realized using a general purpose computer. The invention has application to the estimation of integrated circuit manufacturability, yield and other properties.
REFERENCES:
patent: 5655110 (1997-08-01), Krivokapic et al.
patent: 5822218 (1998-10-01), Moosa et al.
patent: 5960185 (1999-09-01), Nguyen
patent: 5991699 (1999-11-01), Kulkarni et al.
Allan et al. ("Efficient critical area algorithms and their application to yield improvement and test strategies", 1994 Proceedings of the IEEE International Workshop on Defect and fault Tolerance in VLSI Systems, pp. 88-96, Jan. 1, 1994).
C.H. Stapper and R.J. Rosner, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation", IEEE Transactions on Semiconductor Manufacturing, 1995, vol. 8(2), May 1995, pp. 95-102.
G.A. Allan and A.J. Walton, "Hierarchical Critical Area Extraction with the EYE tool", IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, Lafayette, Louisiana, 1995, pp. 28-36.
P.K. Nag and W. Maly, "Hierarchical Extraction of Critical Area for Shorts in very large scale ICs", IEEE Workshop on Defect and Fault Tolerance in VLSI Systems, 1995, Lafayette, Louisiana, pp. 19-27, Jan. 1, 1995.
H.T. Heineken and W. Maly, "Manufacturability analysis environment--MAPEX", Custom Integrated Circuits Conference, San Diego, CA, 1994, pp. 309-312, Jan. 1994.
S.M. Domer, S.A. Foertsch and G.D. Raskin, "Component Level Yield/Cost Model for Predicting VLSI Manufacturability on Designs Using Mixed Technologies, Circuitry, and Redundancy", Custom Integrated Circuits Conference, San Diego, CA, 1994, pp. 313-316, Jan. 1994.
Kik Phallaka
Lintz Paul R.
University of Edinburgh
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