1990-08-07
1992-02-18
Wojciechowicz, Edward J.
357 51, 357 55, H01L 2778
Patent
active
050898698
ABSTRACT:
Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.
REFERENCES:
patent: 4958318 (1990-09-01), Harari
S. Inoue et al., "A Spread Stacked Capacitor (SSC) Cell for 64 mbit DRAMs", International Electron Device Meeting Technical Digest Papers, pp. 31-34 (1989).
H. Watanabe et al., "Stacked Capacitor Cells for High-density Dynamic RAMs", IDEM Digest of Technical Papers (1988), pp. 600-613.
S. Nakajimi et al., "An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM," IEDM Digest of Technical Papers (1988), pp. 240-243.
Inoue Michihiro
Matsuo Naoto
Okada Shozo
Matsushita Electric - Industrial Co., Ltd.
Wojciechowicz Edward J.
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