CMOS sense amplifier with bit line isolation

Details CMOS sense amplifier with bit line isolation CMOS sense amplifier with bit line isolation

1990-02-28

1992-07-07

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365205, G11C 1140

Patent

active

051277395

ABSTRACT:
A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.

REFERENCES:
patent: 3879621 (1975-04-01), Cavaliere et al.
patent: 4418293 (1983-11-01), McAlexander, III et al.
patent: 4658382 (1987-04-01), Tran et al.
patent: 4860255 (1989-08-01), Shimohigashi et al.
Chao et al., "CMOS Sense-Restore Circuits for One-Device Fet Dynamic Ram" IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar. 1983, pp. 5088-5091.

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