Method and apparatus for implementing refresh in a synchronous D

Details Method and apparatus for implementing refresh in a synchronous D Method and apparatus for implementing refresh in a synchronous D

1994-12-02

1995-08-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365212, 365227, G11G 700

Patent

active

054466962

ABSTRACT:
A synchronous DRAM system with internal refresh is controlled by a refresh signal issued by an oscillator or memory controller coupled to the DRAM. By locating the oscillator on the processor or memory controller better control of the frequency of refresh is achieved, particularly, as the signal can be derived from a crystal which is not sensitive to variations in operating conditions. The oscillator drives a refresh signal on a bus or signal line to the DRAM, such that the refresh address counter is incremented and the row identified by the refresh address counter is refreshed.

REFERENCES:
patent: 3796998 (1974-03-01), Appelt
patent: 3800295 (1974-03-01), Anderson, Jr. et al.
patent: 4249247 (1981-02-01), Patel
patent: 4393477 (1983-07-01), Murotani
patent: 4453237 (1984-06-01), Reese
patent: 4459660 (1984-07-01), Bellay
patent: 4631701 (1986-12-01), Kappeler
patent: 4682306 (1987-07-01), Sakurai
patent: 4716551 (1987-12-01), Inagaki
patent: 4881205 (1989-11-01), Aihara
patent: 4901283 (1990-02-01), Hanbury
patent: 5262998 (1993-11-01), Mnich
IBM Technical Disclosure Bulletin, vol. 32, No. 8B, Jan. 1990, pp. 223-224, "Synchronous Memory Refresh Scheme Which Supports Several Refresh Rates Without Jumpers on Cards or Planars."

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