Semiconductor memory having a polycrystalline silicon load resis

Details Semiconductor memory having a polycrystalline silicon load resis Semiconductor memory having a polycrystalline silicon load resis

1994-04-21

1995-08-29

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365181, 257297, 257369, 257904, G11C 11417

Patent

active

054466890

ABSTRACT:
A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

REFERENCES:
patent: 3541530 (1970-11-01), Spampinato et al.
patent: 3560764 (1971-02-01), McDowell
patent: 3813563 (1974-05-01), Hatsukano et al.
patent: 4110776 (1978-08-01), Rao et al.

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