Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-07-22
1999-09-07
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711203, 711205, 711206, 711207, G06F 1202
Patent
active
059502320
ABSTRACT:
A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of which has a plurality of page data. The fetching apparatus is located between the processor and the main memory. The fetching apparatus fetches the page data of a specific one of the pages as fetched page data from the main memory and supplies the fetched page data to said processor. The fetching apparatus comprises a plurality of registers (23-1 to 23-K) each of which is for memorizing the fetched page data. A table section (24) is for memorizing addresses corresponding the page data in each of the page. The table section further memorizes, as data transfer locations, the memory areas corresponding to the addresses. In response to the specific page, a reading section (25) reads the page data of the specific page out of the main memory as read page data with reference to the table section to fetch the read page data as the fetched page data to a specific one of the registers in accordance with a specific one of the data transfer locations.
REFERENCES:
patent: 3909798 (1975-09-01), Wallach et al.
patent: 3976978 (1976-08-01), Patterson
patent: 4403283 (1983-09-01), Myntti
K.J. Thurber, "Programmable indexing networks", Proceedings of the Spring Joint Computer Conference, May 5-7, 1970, pp. 51-58.
Chan Eddie P.
NEC Corporation
Nguyen Than V.
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