Process for reducing program disturbance in EEPROM arrays

Fishing – trapping – and vermin destroying

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437 24, 437 45, 437 48, 437 49, 437979, 437983, 148DIG117, H01L 21265

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052159345

ABSTRACT:
A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.

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patent: 4924437 (1990-05-01), Paterson
"VLSI Technology", edited by Sze, M. C., McGraw Hill Book Company, 1983, pp. 145-149.

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