Semiconductor memory device comprising multi-level logic value o

Details Semiconductor memory device comprising multi-level logic value o Semiconductor memory device comprising multi-level logic value o

1995-08-31

1999-09-07

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257316, H01L 29788

Patent

active

059491019

ABSTRACT:
A semiconductor memory device including a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on the semiconductor substrate. Each memory cell contains a first transistor provided with a gate, and the semiconductor substrate includes element separating trenches arranged at least in part of the respective memory cells and each of the element separating trenches is embedded at least partly with an element separating insulative film. An electrically conductive film is embedded in at least part of the remaining area of the trench, a second transistor is constructed by at least part of the lateral sides of each of the element separating trenches having an embedded conductive film forming a part of a channel region, and a third transistor is constructed by another part of the the lateral sides of each of the element separating trenches forming part of a channel region. Diffusion layers of sources and drains of the second transistor and the third transistor are shared and the second and third transistors are connected in parallel to construct the first transistor of the memory cell. The threshold voltage of the second transistor having the conductive film formed as a second gate is set to a voltage higher than a voltage applied to the second gate selected in a read operation.

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