Reduced capacitance transistor with electro-static discharge pro

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257356, 257358, H01L 2362

Patent

active

058474315

ABSTRACT:
An apparatus is disclosed for providing a reduced-capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate, a source region formed in the substrate, and a well region also formed in the substrate. The transistor further includes a drain region having a first end region, a second end region, and a resistive region positioned between the first and second end regions. The drain region is formed at least partially in the well region. A drain contract is form on the first end region of the drain region. Additionally, a gate structure is included. The gate structure is formed on the substrate between the source region and the second end region of the drain region. The gate structure defines a channel region that couples the source to the drain region.

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