Low overhead input and output boundary scan cells

Details Low overhead input and output boundary scan cells Low overhead input and output boundary scan cells

1996-09-09

1997-12-23

Canney, Vincent P.

Excavating

39518305, G01R 3128

Patent

active

057013071

ABSTRACT:
Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are prodded. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5459737 (1995-10-01), Andrews
Nai-Chi Lee, "A Hierarchical Analog Test Bus Framework for Testing Mixed-Signal Integrated Circuits and Printed Circuit Boards", Journal of Electronic Testing, vol. 4, No. 4, Nov. 1, 1993, pp. 361-368.
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.

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