Semiconductor memory with hierarchical bit lines

Details Semiconductor memory with hierarchical bit lines Semiconductor memory with hierarchical bit lines

1996-06-25

1997-12-23

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 365229, 36523003, G11C 700

Patent

active

057012695

ABSTRACT:
A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.

REFERENCES:
patent: 4644501 (1987-02-01), Nagasawa
patent: 5132931 (1992-07-01), Koker
patent: 5367488 (1994-11-01), An
patent: 5570319 (1996-10-01), Santoro et al.

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