Method of making stacked capacitor DRAM cell

Details Method of making stacked capacitor DRAM cell Method of making stacked capacitor DRAM cell

1989-11-06

1992-06-09

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

051206749

ABSTRACT:
A saddled and wrapped stack capacitor DRAM and a method thereof are provided. The DRAM of the invention includes three foactors in increasing the effective areas for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterned to selectively remove the storage poly layer, and the spacer makes the storage poly to be remained maximize or be proper by controlling the size thereof; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plate poly material is coated and wraps.

REFERENCES:
patent: 3936331 (1976-02-01), Luce et al.
patent: 4214946 (1980-02-01), Forget et al.
patent: 4251571 (1981-02-01), Garbarino et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4871688 (1989-10-01), Lowrey
patent: 5021357 (1991-06-01), Taguchi et al.

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